The acoustic charge transport (ACT) device, described in U.S. Pat. No. 4,633,285, is a high speed GaAs charge transfer device in which electron transport is accomplished using the traveling wave electric field of a UHF surface acoustic wave generated directly in the GaAs. The capability to monolithically integrate conventional active and passive GaAs integrated circuit elements with the ACT device is absolutely critical in advanced applications of the ACT technology. Most advanced ACT device applications, such as programmable ACT signal processors or high performance delay lines and transversal filters, require significant levels of conventional digital and/or analog circuit integration with the ACT device.
A variety of conventional GaAs integrated circuit (IC) methods have been developed and are well known in the art. The most common of these utilizes selective ion implantation in semi-insulating GaAs substrates to spatially define and electrically isolate the semiconducting regions required for individual IC elements. Another common approach involves the epitaxial growth of thin GaAs layers on the semi-insulating substrate coupled with mesa etching or ion bombardment damage techniques to achieve spatial definition and lateral electrical isolation of individual circuit element semiconducting layers. In most cases, the semiconducting regions required for the IC elements are very thin and approximately the same for all elements, thus simplifying the integration process.
In contrast with the conventional GaAs IC technology, the integration of high performance GaAs circuit elements such as Schottky barrier field effect transistors, diodes, and semiconductor resistors with the ACT device presents a significant challenge. This difficulty arises because the semiconductor layer characteristics required to achieve acceptable operation of the ACT device are considerably different from those required to produce acceptable integrated circuit elements. The ACT device channel layer must presently be grown epitaxially to achieve the very high purity required for precision charge transfer and it is relatively thick (typically a few microns) with relatively low n-type carrier concentration (typically 10.sup.15 -10.sup.16 /cm.sup.3) in an optimal design. In comparison, the desired semiconductor layer thickness for active integrated elements, for example an FET, is relatively thin (typically less than a few thousand angstroms) with high n-type or p-type carrier concentration (of the order of 2.times.10.sup.17 /cm.sup.3). Moreover, ion implantation of the dopant is usually preferred in a manufacturable process to take advantage of the superior parameter control and spatial uniformity associated with this approach.
Although a thin, highly doped GaAs layer can be formed at the surface of the ACT layer by conventional ion implantation or epitaxial growth techniques, a fundamental integration difficulty involves the vertical electrical isolation of the layer from the underlying epitaxial material. For example, without vertical isolation, the epitaxial material essentially forms a large vertical extension to the n-channel of a Schottky barrier FET resulting in excessive FET pinch-off voltages and high parasitic shunt conductance between the source and drain terminals of the FET. These effects prohibit the proper operation of the FET. In general, the DC or AC parasitic effects associated with a conductive epitaxial buried layer inhibit or greatly degrade the operation of high speed GaAs integrated circuit elements. These parasitic effects are particularly critical in an ACT integrated circuit because the characteristic impedance levels of the ACT device and its appropriate interface circuits are very high.
A prior ACT integration approach for the FET, which attempts to address the vertical isolation problem, utilizes a p-type implant into the ACT layer to form a shallow p-type tub in which an n-type FET channel is situated. Under proper conditions, this configuration can provide the necessary pinchoff voltage isolation through the potential barrier associated with the zero or reversed biased p-n junction but it also produces an undesirable fundamental tradeoff between two key performance parameters of the FET. In particular, it is found that the low p-layer acceptor sheet carrier concentration regime (corresponding to nearly complete p-layer thermal depletion via its adjacent pn junctions) produces a DC punch-through effect at unacceptably low drain-source voltages which effectively destroys the intended vertical isolation from the underlying epitaxial layer. Alternatively, the large acceptor sheet carrier concentration regime (which eliminates the punch-through problem by expanding the drain-source punch-through voltage to levels beyond the intended operating range of the FET ) produces an unacceptably large value of AC drain-source conductance due to the capacitive coupling of the FET channel to the underlying conductive p-layer. Because the degrading effects of these regimes tend to overlap, no p-tub structure design which provides an acceptable compromise to these competing effects has been found. In addition, since this approach results in p-type or n-type conductive buried layers under other integrated circuit elements as well, general circuit element performance is degraded by parasitic effects.
Short et al. investigated the use of O and He compensation implants for tailoring the doping profiles associated with implanted layers in semi-insulating GaAs substrates.
Chand et al. have described a process which provides a minimal level of DC vertical electrical isolation for an implanted FET in an undoped GaAs epitaxial buffer layer. This process utilizes a relatively low dose oxygen compensating implant in the active region of the FET to create a thin (several thousand angstroms) semi-insulating layer beneath the implanted channel layer of the FET. It was found that the oxygen implant created undesirable damage of the FET channel layer and a high temperature anneal at 500.degree. C. was required to mitigate this effect. It was also reported that the degree of electrical isolation achieved with this process was inferior to that associated with implanted semi-insulating substrate technology despite the relatively low conductivity of the undoped buffer layer. This prior epitaxial implant process cannot be successfully used for ACT compatible circuit element integration because the penetration depths of the compensating ions are roughly an order of magnitude less than that required for effective vertical isolation of the thick conductive ACT epitaxial layer. Although a thin semi-insulating vertical isolation layer can be produced by this process, circuit element structures isolated by this technique are susceptible to the same DC punch-through and AC parasitic effects described for the p-tub approach due to the presence of the underlying epitaxial layer.
The use of proton implants for lateral electrical isolation of integrated ciruit components in the monolithic plane of semiconductor substrates is well known. It is generally understood that the electrical isolation is obtained from the carrier compensation effects of energy states deep in the band gap (deep traps) resulting from the crystal damage associated with the particle bombardment. The typical application of this technique involves the selective implant of protons in all regions of the integrated circuit which are not occupied by semiconductor based circuit elements.
The use of ion implantation for device isolation is well established in microcircuit fabrication technology. There, an energetic implant is done to create fully isolated layers, between devices for example. Lateral isolation is the object of that process, which has been widely reported in the scientific literature.
Another type of FET using implant isolation is described in a report by Pruniaux et al (Proc. 2nd International Conf. on Ion Implantation in Semiconductors, Springer Verlag, N.Y., 1971). In this implementation, a thin insulating region is produced with a low energy proton implant between the FET's gate and its active channel. This work appears to have little relevance to the disclosed invention.
Other reports have used hydrogen for FET fabrication, but in a chemical, donor neutralizing fashion as opposed to making use of the crystal damage associated with bombardment with high energy protons. The donor neutralization technique is not known to provide depth selectivity.